A conventional integrated circuit device may include a plurality of output driver circuits that are configured to drive on-chip or off-chip loads at high data rates. These output driver circuits may be single stage devices having a pull-down transistor connected to a pull-up load (e.g., resistor, depletion-mode transistor, etc.). The pull-down transistor may have a gate terminal responsive to an input signal, a drain terminal coupled to an output of the driver circuit and a source terminal coupled to a reference supply line (e.g., Vss). The resistor may be electrically coupled between the output of the driver circuit and a positive power supply line (e.g., Vdd). During operation, the input signal may have a full swing width and thereby swing rail-to-rail between Vss and Vdd. The output signal at the output of the driver circuit may also have a full swing width. One example of a conventional output driver circuit is disclosed in U.S. Pat. No. 6,130,563.
A single stage output driver circuit may utilize a large pull-down transistor in order to drive a high capacitance load with an output signal having a full swing width. Unfortunately, using such a large pull-down transistor to switch an output signal rail-to-rail may limit an operating speed of the output driver circuit. To address this speed limitation, output driver circuits having multiple stages have been developed for high speed applications. In such driver circuits, the signal swing widths of the signals generated at the outputs of one or more of the stages may be smaller to thereby support higher switching rates.
FIG. 1 is an electrical schematic of a conventional output driver circuit 10 having multiple driver stages. These stages are illustrated as an input driver stage 12, an intermediate driver stage 13 and an output driver stage 14. An input buffer 11 (e.g., inverter) is also provided for buffering a data input signal DIN. As illustrated, the input driver stage 12 includes an NMOS pull-down transistor NM1 and a pull-up resistor R1. The gate terminal of the NMOS pull-down transistor NM1 receives a complementary data input signal DINB generated by the input buffer 11. The intermediate driver stage 13 includes an NMOS pull-down transistor NM2 and a pull-up resistor R2. The gate terminal of the NMOS pull-down transistor NM2 is electrically coupled to an output (e.g., drain terminal of NMOS transistor NM1) of the input driver stage 12. The output driver stage 14 includes an NMOS pull-down transistor NM3 and a pull-up/termination resistor R3. The gate terminal of the NMOS pull-down transistor NM3 is electrically coupled to an output (e.g., drain terminal of NMOS transistor NM2) of the intermediate driver stage 13. The value of the pull-up/termination resistor R3 is typically chosen to match a resistance of a load (not shown) being driven by the output DOUT of the output driver stage 14 and thereby inhibit signal reflection at the output DOUT. The resistance values of the pull-up resistors R1 and R2 are typically chosen at relatively small values (e.g., 50 or 75 ohms) so that the swing widths of the signals at the outputs of the input driver stage 12 and the intermediate driver stage 13 are less than rail-to-rail.
As will be understood by those skilled in the art, the swing width of the signal at the output of the input driver stage 12 will range from a maximum voltage of Vdd when the NMOS pull-down transistor NM1 is off to a minimum voltage of Vdd(RNM1/(R1+RNM1)) when the NMOS pull-down transistor NM1 is on. The value RNM1 designates an on-state resistance of the NMOS pull-down transistor NM1. Because the minimum voltage of the signal at the output of the input driver stage 12 may prevent the NMOS pull-down transistor NM2 from completely turning off, the swing width of the signal at the output of the intermediate driver stage 13 will range from a maximum voltage of less than Vdd to a minimum voltage of Vdd(RNM2/(R2+RNM2)) when the NMOS pull-down transistor NM2 is turned on fully. The value RNM2 designates an on-state resistance of the NMOS pull-down transistor NM2. The relatively small swing width of the signal at the output of the intermediate driver stage 13 translates to an even smaller swing width of the output signal DOUT.
FIG. 2 is an electrical schematic of a conventional output driver circuit 20 that generates a pair of differential output signals TXN and TXP in response to a pair of differential input signals DP and DN. This output driver circuit 20 includes first and second bias transistors NM13 and NM14, which are responsive to a bias signal Vb, and first and second input transistors NM11 and NM12, which have commonly connected source terminals. The first and second bias transistors NM13 and NM14 operate as current sources that establish first and second pull-down currents I1 and I2. The output driver circuit 20 also includes first and second load resistors R11 and R12, which are coupled to a pair of outputs OUT1 and OUT2. Based on this configuration of the output driver circuit 20, the swing widths of the output signals TXN and TXP will be a function of the values of the load/termination resistors R11 and R12 (e.g., 50 or 75 ohms) and the values of the pull-down currents I1 and I2.
FIG. 3 is an electrical schematic of a conventional input circuit 30 and input signal sampler 40, which generates an input signal IN_DAT. As illustrated, the input circuit 30 includes a pair of termination resistors R21 and R22, a pair of load resistors R31 and R32 and NMOS transistors NM21, NM22 and NM23. The gate terminals of the NMOS transistors NM21 and NM22 receive a pair of differential input signals RXP and RXN at the inputs IN1 and IN2. The NMOS transistor NM23, which is responsive to a clock signal CLK, operates as an enable transistor that determines when the input circuit 30 is active. The signal swing widths of these input signals is influenced by the values of the termination resistors R21 and R22, which may have relatively small values (e.g., 50 or 75 ohms). The drain terminals of the NMOS transistors NM21 and NM22 develop a pair of differential signals, which are provided as inputs to the sampler 40.
Unfortunately, although the generation of signals having relatively small swing widths may increase the operating speeds of driver circuits, these small swing widths may complicate testing of integrated circuits at the wafer level if the swing widths are insufficient to be reliably detected by test equipment. Thus, notwithstanding the performance advantages provided by driver circuits having small swing widths, there continues to be a need for driver circuits that support small swing widths and also support reliable testing at the wafer level.